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Synchronizing Sine Wave PWM across the Inverters

A simple RMS matched PWM equivalent sinewave waveform generator can be made by using an IC 555 and IC 4060, as shown in the following figure.

This design can be then used for enabling the inverters to produce a sinewave equivalent waveform at their outputs, and across the connected mains line.

Each of these PWM processors would be required for each of the stackable inverter modules individually.






The different stages involved in the above PWM geneartor circuit can be understood with the help of the following point:

The IC 555 is configured as the basic PWM generator circuit. To be able to generate an adjustable PWM equivalent pulses at the desired RMS the IC requires fast triangle waves at its pin7 and a reference potential at its pin5 which determines the PWM level at its output pin#3

For generating the triangle waves, the IC 555 requires square waves at its pin#2, which is acquired from the IC 4060 oscillator chip.

The IC 4060 determines the frequency of the PWM, or simply the number of "pillars" in each of the AC half cycles.

The IC 4060 is mainly employed for multiplying the sample low frequency content from the inverter output into a relatively high frequency from its pin#7. The sample frequency basically makes sure that the PWM chopping is equal and synchronized for all the invetrer modules. This is main reason why the IC 4060 is included otherwise another IC 555 could have easy done the job, instead.

The reference potential at pin#5 of IC 555 is acquired from an opamp voltage follower shown at extreme left of the circuit.

As the name suggests this opamp delivers exactly the same magnitude of voltage at its pin#6 which appears at its pin#3....however the pin#6 replication of its pin#3 is nicely buffered, and therefore is richer than its pin3 quality, and thats the exact reason of including this stage in the design.

The 10 k preset associated at pin3 of this IC is used for adjusting the RMS level which ultimately fine tunes the the IC 555 output PWMs to the desired RMS level.

This RMS is then applied to the bases of the power devices in order to force them to work at the specified PWM RMS levels, which in turn causes the output AC to acquire a pure sinewave like attribute through a correct RMS level. This may be further enhanced by employing an LC filter across the output winding of the all the transformers.

The next and the final part of this 4kva stackable synchronized inverter circuit details the automatic load correction feature for enabling the inverters to deliver and maintain the correct amount wattage across the output power mains line in accordance with the varying loads switching.

We have so far covered the two main requirements for the proposed synchronized 4kva stackable inverter circuit, which includes synchronization of frequency, phase and PWM across the inverters so that failing of any of the inverters had no effect on the rest in terms of the above parameters.


In this article we will try to figure out the automatic load correction feature which may enable the switching ON or OFF of the inverters sequentially in response to the varying load conditions across the output mains line.

A simple quad comparator using LM324 IC can be used for implementing an automatic sequential load correction as indicated in the following diagram:



In the figure above we can see four opamps from the IC LM324 configured as four separate comparators with their non-inverting inputs rigged with individual presets,while their inverting inputs all referenced with a fixed zener voltage.

The relevant presets are simply adjusted such that the opamps produce high outputs in a sequential a soon as the mains voltage goes above the intended threshold..... and vice versa.

When this happens the relevant transistors switch in accordance with the opamp activation.

The collectors of the respective BJTs are connected with the pin#3 of the voltage follower opamp IC 741 which is employed in the PWM controller stage, and this forces the opamp output to go low or zero, which in turn causes a zero voltage to appear at pin#5 of the PWM IC 555 (as discussed in Part 2).

With pin#5 of the IC 555 is applied with this zero logic, forces the PWMs to become narrowest or at the minimum value, which causes the output of that particular inverter to almost shut down.

The above actions make an attempt to stabilize the output to an earlier normal condition which again forces the PWM to get wider and this tug-of-war or a constant switching of the opamps cintinues consistently keeping the output as stable as possible, in response to the variations of the attached loads.

With this automatic load correction implemented within the proposed 4kva stackable inverter circuit almost makes the design complete with all the features requested by the user in Part 1 of the article.

In this write-up we try to understand in detail regarding the various possible faults that could be encountered while constructing the proposed sinewave UPS circuit using PIC16F72. and how to troubleshoot these issues effectively through simple steps.

Data provided by: Mr. hisham bahaa-aldeen (hisham2630@gmail.com)

Sinewave UPS Circuit using PIC16F72 Part-1
 
Sinewave UPS Circuit using PIC16F72 Part-2
 
Sinewave UPS Circuit using PIC16F72 Part-3
 
Sinewave UPS Circuit using PIC16F72 Part-4

SINEWAVE UPS TESTING AND FAULT FINDING

Construct the card thereby confirming each and every wiring, this includes LED connectivity, ON/OFF switch, feedback via inverter transformer, 6-volt mains sense to CN5, -VE of battery to card, +VE of battery to large heatsink.

Initially do not plug the transformer primary to the pair of small heat sinks.

Plug in battery +ve wire to PCB via MCB and 50-amp ammeter.

Prior to proceeding for the recommended testings be sure to check the +VCC voltage at the pins of U1 - U5 in the following sequence.

U1:pin#8 and 9: +5V, pin#3: +12V, pin#6: +12V, U2:pin#8 and 9: +5V, pin#3: +12V, pin6: +12V, U3: pin14: +5V, U4: pin20: +5V, pin1:+5V, U5: pin4:+5V.

1) Power Up the battery MCB and check the ammeter and also be certain it doesnt jump beyond 1-amp. If the ampere shoots then remove U1 and U2 briefly and switch ON the MCB again.


 2) Power ON by toggling the given ON/OFF switch of the inverter and check whether or not the relay clicks ON, illuminating the "INV" LED. If it doesnt then check the voltage at pin#18 of the PIC which is supposed to be 5V. If this is absent check components R37 and Q5, one of this may be faulty or incorrectly connected. If you find the "INV" LED not switching ON, check if the voltage at pin#25 of the PIC is 5V or not.

 If the above situation is seen to be normally executing, go to the next step as described below.

3) Using an oscilloscope test pin#13 of the PIC by alternately switching ON/OFF the inverter switch, you can expect to see a well modulated PWM signal appearing at this pinout each time the inverter mains input is switched OFF, if not then you can assume the PIC to be faulty, coding not implemented correctly or the IC is badly soldered or inserted in its socket.

If you succeed in getting the expected modified PWM feed over this pin, go to pin#12/in#14 of the IC and check the availability of 50Hz frequency on these pins, if not would indicate some fault in the PIC configuration, remove and replace it. If you are to get affirmative response on these pins, go to the next step as explained below.

4) The next step would be to test pin#10/pin#12 of the IC U3 (CD4081) for the modulated PWMs which are finally integrated with the mosfet driver stages U1 and U2. Additionally you would be also required to check the potential differences at pin#9/pin#12 which is supposed to be at 3.4V approximately, and at pin#8/pin#13 may be verified to be at 2.5V. Similarly verify pin#10/11 to be at 1.68V.

In case you fail to identify the modulated PWM across the CD4081 output pins, then you would want to verify the tracks terminating to the relevant pins of the IC CD4081 from the PIC, which could be broken or somehow the obstructing the PWMs from the reaching U3.
If all is fine, lets move to the next level.

 5) Next, attach the CRO with U1 gate, toggle the inverter ON/OFF and as done above verify the PWMs on this spot which are M1 and M4, and also the gates M9, M12, however dont be surprised if the PWM switching are seen out of phase M9/M12 as compared to M1/M4, thats normal.

If the PWMs are entirely absent on these gates, then you can check pin#11 of U1 which is expected to be low, and if found high would indicate that U1 may be running in the shut-down mode. To confirm this situation check voltage at pin#2 of U5 which could be at 2.5V, and identically pin#3 of U5 could be at 0V or under 1V, if its detected to be below 1V, then proceed and check R47/R48, but if the voltage is found to be above 2.5V then check D11, D9, along with mosfets M9, M12 and the relevant components around it to troubleshoot the persisting issue, until corrected satisfactorily..

 In case where the pin#11 of U1 is detected low and still you are unable to find the PWMs from pin#1, and pin#7 of U1, then its time to replace IC U1, which would possibly rectify the issue, which will prompt us to move to the next level below.

6) Now repeat the procedures exactly as done above for the gates of the mosfet array M5/M18 and M13/M16, the troubleshooting would be exactly as explained but with reference to U2 and the other complimentary stages which may be associated with these mosfets

7) After the above testing and confirmation are completed, now its finally time to hook up the transformer primary with the mosfet heatsinks as indicated in the sinewave UPS circuit diagram. Once this is configured, switch ON the inverter switch, adjust preset VR1 to hopefully access the required 220V regulated, constant sinewave AC across the output terminal of the inverter.
If you find the output to be exceeding this value or below this value, and void of the expected regulation, you may look for the following issues:
If the output is much higher, check voltage at pin#3 of the PIC which is supposed to be at 2.5V, if not then verify the feedback signal derived from the inverter transformer to connector CN4, further check voltage across C40, and confirm the correctness of the components R58, VR1 etc. until the issue is rectified.

8) After this attach an appropriate load to the inverter, and check the regulation, a 2 to 3 percent falter can eb considered normal, if still you fail a regulation, then check diodes D23----D26, you can expect one of these to be faulty or you may also try replacing C39, C40 for correcting the issue.

9) Once the above procedures are successfully completed, you can carry on by checking the LOW-BATT functioning. To visualize this try short circuiting R54 with the help of a pair of tweezers from the component side, which should instantly prompt the LOW-Batt LED to illuminate and the buzzer to beep for a period of around 9 seconds at the rate of  a beep per second approximately.

In case the above does not happen, you may check pin#4 of the PIC, which should be normally at above 2.5V, and anything lower than this triggers the low batt warning indication. If an irrelevant voltage level is detected here check whether or not R55 and R54 are in a correct working order.

10) Next up it would be the overload tripping feature which would need to be confirmed. For testing you can select a 400 Wait incandescent bulb as the load and connect it with the inverter output. Adjusting VR2 the overload tripping should initiate at some point on the preset rotation.
To be precise, check the voltage at pin#7 of the PIC where under correct load conditions the voltage will be over 2V, and anything above this level will trigger overload cut-off action.
With a sample 400 watt, try varying the preset and try forcing an overload cut -off to initiate, if this does not happen, verify voltage at pin#14 of U5 (LM324) which is supposed to be higher than 2.2V, if not then check R48, R49, R50 and also R33 any of these could be malfunctioning, if everythings correct here simply replace U5 with a new IC and check the response.
Alternatively you can also try increasing the R48 value to around 470K or 560k or 680K etc and check if it helps solving the issue.

11) When the assessment of inverter processing is finished, experiment with the mains changeover.Keep the mode switch in inverter mode (keep CN1 open) switch-ON the inverter, hook up the mains wire to the variac, step up the variac voltage to 140V AC and check the inv to mains changeover triggering occurs or not. If you find no changeover in that case confirm the voltage at pin2 of microcontroller, it needs to be > 1.24V, in case the voltage is smaller than 1.24V then inspect the sensing transformer voltage (6V AC at its secondary) or take a look at the components R57,R56.

Now that the changeover shows up scale down the variac voltage to below 90V and examine the mains-to-inverter changeover action is established or not. The changeover ought to happen since now the voltage at pin2 of microcontroller is less than 1V.

12) Soon after the above assessment is completed, experiment with the mains-changeover in the UPS mode. Enabling the mode-switch in the UPS mode (keep CN1 shorted) start the inverter, link up the mains wire to the variac, increment the variac voltage to around 190V AC and observe the UPS-to-mains changeover strikes or not. Should there be no changeover action then simply take a look at the voltage at pin2 of microcontroller, it needs to be over 1.66V, as long as the voltage is lower than 1.66V then simply confirm the sensing transformer voltage (6V AC at its secondary) or perhaps inspect the elements R57,R56.

Right after the changeover pops up, scale back the variac voltage to 180V and find out whether the mains-to-UPS changeover comes about or not. The changeover ought to strike since now the voltage at pin2 of microcontroller could be witnessed to be over 1.5V.

13) Eventually take a look at the customized charging of the attached battery. Hold the mode switch in the inverter-mode, administer mains and step up the variac voltage to 230V AC, and determine the charging current which should rise smoothly in ammeter.

Fiddle with the charging current by varying VR3, so that the current variation could be witnessed varying in the middle of around 5-amp to 12/15-amp. Just in case the charging current is seen to be much higher and not in a position to be scaled down at preferred level then you may try increasing the value of R51 to 100k and/or if still that does not improve the charging current to expected level then perhaps you can try decreasing the value of R51 to 22K, please bear in mind that once the sensed equivalent voltage at pin5 of microcontroller becomes at 2.5V the microcontroller may be expected to regulate the PWM and consequently the charging current.

In the course of the charging mode remember that, precisely the lower branch of MOSFETs (M6 -M12 / M13 - M16) are switching @8kHZ while the upper branch of MOSFETs are OFF.

14) Additionally you can inspect the operation of the FAN, FAN is ON each time the inverter is ON, and FAN could be seen switched OFF whenever the inverter is OFF. In a similar manner FAN is ON as soon as Charging is ON and FAN will be OFF when charging is OFF

In this post we study the mosfet switching stage built for the proposed sinewave UPS circuit using PIC16F72.

Data provided by: Mr. hisham bahaa-aldeen (hisham2630@gmail.com)


Sinewave UPS Circuit using PIC16F72 Part-1
 
Sinewave UPS Circuit using PIC16F72 Part-3
 
Sinewave UPS Circuit using PIC16F72 Part-4

MOSFET Switching:

Check with MOSFET switching circuit diagram below:





In this case U1 (IR2110) and U2 (IR2110) high side / low side mosfet driver are employed, check with data sheet of this IC to understand more. In this the two MOSFET banks with high side and low side MOSFETs are intended for transformer’s primary side switching.

In this case we are discussing the functioning of bank (applying IC U1) only since the supplementary bank driving does not differ from from each other.


As soon as the inverter is ON the controller renders the pin10 of U1 is logic high which subsequently activates the high side MOSFETs (M1 - M4) ON, PWM for channel-1 from pin10 of CD4081 is applied to pin12 of the drver IC (U1) and likewise it is administered to the base of Q1 via R25.

While the PWM is logic high the pin12 of U1 is also logic high and triggers the low side MOSFETs of bank 1(M9 - M12), alternately it launches the transistor


Q1 which correspondingly renders the pin10 voltage of U1 logic low, thereupon turning OFF the high side MOSFETs (M1 - M4).


Therefore it implies that by default the high logic from pin11 of the microcontroller gets switched ON for the high side MOSFETs among the two the mosfet arrays, and while the associated PWM is high the low side MOSFETs are turned ON and the high side MOSFETs are switched OFF, and through this way the switching sequence keeps repeating.

Mosfet Switching Protection


Pin11 of U1 can be used for executing the hardware locking mechanism of each of the drivers units.

By standard fixed mode this pin may be seen fixed with a low logic, but whenever under any circumstance the low side MOFET switching fails to initiate (lets assume through o/p short circuit or erroneous pulse generation at the output), the VDS voltage of low side MOSFETs can be expected to shoot up which immediately causes the output pin1 of comparator (U4) to go high and become latched with the help of  D27, and render pin11 of U1 and U2 at high logic, and thereby toggle OFF the two the MOSFET driver stages effectively, preventing the MOSFETs from getting burnt and damaged.


Pin6 and pin9 is of +VCC of the IC (+5V), pin3 is of +12V for MOSFET gate drive supply, pin7 is the high side MOSFET gate drive, pin5 is the high side MOSFET receiving route, pin1 is the low side MOSFET drive, and pin2 is the low side MOSFET receiving path. pin13 is the ground of the IC (U1).

In this page we learn specifically about the battery charging operations using PWM technique as configured for the proposed sinewave UPS circuit using PIC16F72.


Data provided by: Mr. hisham bahaa-aldeen (hisham2630@gmail.com)


Sinewave UPS Circuit using PIC16F72 Part-1
 
Sinewave UPS Circuit using PIC16F72 Part-2
 
Sinewave UPS Circuit using PIC16F72 Part-3

 

BATTERY CHARGING:

In the course of MAINs ON Battery charging may be seen initiated. As we may understand while in battery charging mode the system may be functioning using the SMPS technique, let us now understand the working principle behind it.


To charge the battery the output circuit (MOSFET and Inverter transformer) becomes effective in the form of a boost converter.


In this case all the low side MOSFETs of the two the mosfet arrays work in sync as a switching stage while the primary of the inverter transformer behave as an inductor.

As soon as all of the low side MOSFETs are switched-ON the electric power gets accumulated in the primary section of transformer, and as soon as the MOSFETs are OFF this accumulated electric power is rectified by the in-build diode inside the MOSFETs and the DC is kicked back to battery pack, the measure of  this boosted voltage would depend on the ON-time of the low side MOSFETs or simply mark/space ratio of the duty cycle used for the charging process.

PWM WORKING

While the equipment may be conducting in the mains-on mode, the charging PWM (from pin13 of micro) is progressively augmented from 1% to highest specification, in case the PWM raises the DC voltage to the battery, the battery voltage too increases which results in a surge in the battery charging current.

The battery charging current is monitored across the DC fuse and negative rail of the PCB and the voltage is additionally intensified by the amplifier U5 (pin8, ppin9 and pin10 of the comparator) this amplified voltage or detected current are applied to the pin5 of microcontroller.

This pin voltage is scheduled in software in the form of 1V, as soon as the voltage in this pin is rises above 1V the controller may be seen restricting the PWM duty cycle until finally its pulled down to below 1V, assuming the voltage on this pin is decreased to below 1V the controller would instantly begin improving the full PWM output, and the process may be expected to go on in this manner with the controller upholding the voltage on this pin at 1V and consequently the charging current limit.

The proposed sinewave inverter UPS circuit is built using PIC16F72 microcontroller, some passive electronic components and associated power devices.

Data provided by: Mr. hisham bahaa-aldeen (hisham2630@gmail.com)


Sinewave UPS Circuit using PIC16F72 Part-2
 
Sinewave UPS Circuit using PIC16F72 Part-3
 
Sinewave UPS Circuit using PIC16F72 Part-4


Main Features:

The main technical features of the discussed PIC16F72 sinewave inverter may be evaluated from the following data:

Power output (625/800va) fully customization and can be upgraded to other desired levels.
Battery 12V/200AH
Inverter Output Volt : 230v (+2%)
Inverter Output Frequency : 50Hz
Inverter Output Waveform : PWM Modulated Sinewave
Harmonic Distortion : less  than 3%
Crest Factor : less than 4:1
Inverter efficiency : 90% For 24v System, around 85% with 12v System
Audible Noise : less 60db At 1-meter


Inverter Protection Features

Low-battery Shut-down
Overload Shut-down
Output Short Circuit Shut-down


Low-battery Detection and Shutdown Feature

Beep Start initiated at 10.5v (beep At Every 3-sec)
Inverter Shut-down at around 10v (5 pulses of beep in every 2-sec)
Over Load : Beep Initiated at 120% Load (beep at the rate of 2-sec)
Inverter Shut-down at 130% Overload (5 pulses of beep in every 2-sec)


LED Indicators are provided for the following:
Inverter On
Low-battery - Flashing in Low battery mode with Alarm
Solid ON During Cut-OFF
Over Load - Flashing at Overload cut-off with Alarm
Solid ON During Cut-OFF
Charging mode - Flashing at Charging mode
Solid ON During Absorption
Mains Indication - LED On


Circuit Specifications

8-bit Microcontroller Based Control Circuit
H-bridge Inverter Topology
Mosfet Switching Fault Detection
Charging Algorithm : Mosfet PWM based switch mode Charger Controller 5-amp/15-amp
2-step Charging Step-1: Boost Mode (led Flash)
Step-2: Absorption Mode (led On)
DC Fan initialization for Internal Cooling During Charging/inv Operation

Circuit Diagram:

PIC Codes can be viewed HERE

PCB details are provided HERE

The following explanation provides the details of the various circuit stages involved in the design:

In Inverter Mode

As soon as mains fails, the battery logic is detected at pin#22 of the IC which instantly prompts the controller section to switch the system in the inverter/battery mode.

In this mode the controller begins generating the required PWMs via its pin#13 (ccp out), however the PWM generation rate is implemented only after the controller confirms the logic level at pin#16 (INV/UPS switch).

If a high logic is detected at this pin (INV mode) the controller initiates a fully modulated duty cycle which is around 70%, and in case of a low logic at the indicated pinout of the IC, then the controller may be prompted to generate burst of PWMs ranging from 1% to 70% at a rate of 250mS period, which is termed as soft delay output while in the UPS mode.

The controller simultaneously with the PWMs also generates a "channel select" logic through pin#13 of the PIC which is further applied to pin#8 of the IC CD4081.

Throughout initial time period of the pulse (i.e 10ms) the pin12 of the PWM controller is rendered high such that the PWM can be obtained from pin10 of CD4081 exclusively and after 10mS, pin14 of controller is logic high and the PWM is accessible from pin11 of CD4081, as a result using this method a pair of anti-phased PWM becomes accessible to switch on the MOSFETs.


Aside from that a high logic (5V) becomes accessible from pin11 of the PWM controller, this pin turns high each time inverter is ON and ends up being low whenever inverter is OFF. This high logic is applied to pin10 of each the MOSFET drivers U1 and U2, (HI pin) to activate the high side MOSFETs of the two the mosfet banks.


For upgrading the proposed Sinewave UPS using PIC16F72, the following data may be used and implemented appropriately.



 The following data supplies the full transformer winding details:

Feedback from Mr. Hisham:

Hi mr swagatam ,how are you? 

I want to tell you that pure sine wave inverter using pic16f72 schematic have some mistakes,220uf bootstrap capcitor should be replaced with a (22uf or 47uf or 68uf),,,a 22uf capacitors which is connected between pin 1 and pin2 of the 2s ir2110 is wrong and should be removed, also a hex code called eletech. Hex should not be use cause its make inverter shutdown after 15 seconds with low battery led and buzer beeps, if you have big dc fan so the transistors should be replaced with a higher current,for mosfets safety a 7812 regulator is recommended to be connected to ir2110...also theres d14,d15 and d16 should not be connected to ground.

I have tested this inverter and its really pure sine wave,i have run a washing machine and its running silently without any noise, i have connected a 220nf capcitor in the ouput instead of 2.5uf, refrigerator is working too, i will share some pictures soon.
Best regards

 

  The schematic discussed in the above article was tested and modified with a few appropriate corrections by Mr. Hisham, as shown in the following images, viewers can refer to these for improving the performance of the same:

The previous post explained the datasheet of the precision capacitive touch/proximity sensor IC PCF8883, here we learn a typical circuit configuration using the same IC which can be applied in all products requiring precision remote touch stimulated operations.
 


The proposed capacitive touch and proximity sensor may be diversely used in many different applications as indicated in the following data:




A typical application configuration using the IC can be witnessed below:






The + input supply is attached with the VDD. A smoothing capacitor may be preferably connected across and VDD and ground and also across VDDUNTREGD and ground for more reliable working of the chip.

The capacitance value of COLIN as produced on pin CLIN fixes the sampling rate effectively. Increasing sampling rate may enable enhance reaction time on the sensing input with a proportionate increase in the current consumption

The sensing capacitive touch plate could be in the form of a miniature metal foil or plate shielded and isolated with a non conductive layer.

This sensing area could be either terminated over a longer distances via a coaxial cable CCABLE whose other ends may be linked with the IN of the IC, or the plate could be simply directly connected with the INpinout of the IC depending on the application needs.

The IC is equipped with an internal low pass filter circuitry which helps to suppress all forms of RF interferences that may try to make way in to the IC through the IN pin of the IC.

Additionally as indicated in the diagram one may also add an external configuration using RF and CF to further enhance the RF suppression and reinforce RF immunity for the circuit.

In order to achieve an optimal performance from the circuit, its recommended that the sum of the capacitance values of CSENSE + CCABLE + Cp should be within a given appropriate range, a good level could be around 30pF.

This helps the control loop to work in a better way with the static capacitance over CSENSE for equalizing the rather slower interactions on the sensing capacitive plate.


For achieving an increased levels of capacitive inputs it may be recommended to include a supplementary resistor Rc as indicated in the diagram which helps to control the discharge time as per the internal timing requirement specs.

The cross sectional area of the attached sensing plate or a sensing foil becomes directly proportional to the sensitivity of the circuit, in conjunction with the value of the capacitor Ccpc, reducing Ccpc value can greatly affect the sensitivity of the sensing plate. Therefore for achieving an effective amount of sensitivity, Ccpc could be increased optimally and accordingly.

The pinout marked CPC is internally attributed with a high impedance and therefore could be susceptible to leakage currents.

Make sure that Ccpc is chosen with a high quality PPC of MKT type of capacitor or X7R type for obtaining optimal performance from the design.

In case the system is intended to be operated with a restricted input capacitance of upto 35pF and at freezing temperatures -20 degrees C, then it may be advisable to bring down the supply voltage to the IC to around 2.8V. This in turn brings down the operating range of Vlicpc voltage whose specification lies between 0.6V to VDD - 0.3V.

Moreover, lowering the operating range of Vucpc could result in lowering the input capacitance range of the circuit proportionately.

Also, one may notice that as Vucpc value increases with decreasing temperatures as demonstrated in the diagrams, which tells us why appropriately lowering the supply voltage helps in decreasing temperatures.

Table 6 and Table7 indicates the recommended range of the components values which may be appropriately chosen as per the desired application specifications with reference to the above instructions.






Reference: PCF8883 data sheet

The IC PCF8883 is designed to work like a precision capacitive touch and proximity sensor switch through a unique (EDISEN patented) digital technology for sensing the minutest difference in the capacitance around its specified sensing plate.


The main features of this specialized capacitive touch and proximity sensor can be studies as given below:


 The following image shows the internal configuration of the IC PCF8883



The IC doesnt rely on the traditional dynamic capacitance mode of sensing rather detects the variation in the static capacitance by employing automatic correction through continuous auto-calibration.

The sensor is basically in the form of a small conductive foil which may be directly integrated with the relevant pinouts of the IC for the intended capacitive sensing or perhaps terminated to longer distances through coaxial cables for enabling accurate and effective remote capacitive touch sensing operations

The following figures represent the pinout details of the IC PCF8883. The detailed functioning of the various pinouts and the in-built circuitry may be understood with the following points:

A typical application configuration can be studied through this capacitive touch/proximity sensorcircuit design

The pinout IN which is supposed to be connected with the external capacitive sensing foil is linked with the ICs internal RC network.

The discharge time given by "tdch" of the RC network is compared by the discharge time of the second in-bult RC network denoted as "tdchimo".

The two RC networks go through periodic charging by VDD(INTREGD) through a couple of identical and synchronized switch networks, and subsequently discharged with the help of a resistor to Vss or the ground

The rate at which this charge discharge is executed is regulated by a sampling rate denoted by "fs".

In case if the potential difference is seen to be dropping below the internally set reference voltage VM, the corresponding output of the comparator tends to become low. The logic level which follows the comparators identifies the exact comparator that actually could switch before the other.

And if the upper comparator is identified to have fired first, this results with a pulse being rendered on CUP, whereas if the lower comparator is detected to have switched prior to the upper, then the pulse is enabled at CDN.


The above pulses engage in controlling the charge level over the external capacitor Ccpc associated with pin CPC. When a pulse is generated on CUP, the Ccpc is charged through VDDUNTREGD for a given period of time which triggers a rising potential on Ccpc.

Quite on the same lines, when a pulse is rendered at CDN, the Ccpc gets linked with current sink device to ground which discharges the capacitor causing its potential to collapse.

Whenever the capacitance at pin IN gets higher, it correspondingly increases the discharge time tdch, which causes the voltage across the relevant comparator to fall at a correspondingly longer time. When this takes place the output of the comparator tends to get low which in turn renders a pulse at CDN forcing the external capacitor CCP to discharge to some smaller degree.

This implies that CUP now generates the majority of the pulses which causes CCP to charge up even more without going through any further steps.

Inspite of this, the automatic voltage controlled calibration feature of the IC which relies on a sink current regulation "ism" associated with pin IN makes an effort to balance out the discharge time tdch by referring it with an internally set discharge time tdcmef.

The voltage across Ccpg is current controlled and becomes responsible for the discharge of the capacitance on IN rather rapidly whenever the potential across CCP is detected to be increasing. This perfectly balances the increasing capacitance on input pin IN.

This effect give rise to a closed loop tracking system which continuously monitors and engages into an automatic equalizing of the discharge time tdch with reference to tdchlmf.

This helps to correct sluggish variations in capacitance across IN pinout of the IC. During rapidly charging sates for example when a human finger is approached the sensing foil quickly, the discussed compensation might not transpire, in equilibrium conditions the length of the discharge period do not differ causing the pulse to alternately fluctuate across CUP and CDN.


This further implies that with larger Ccpg values a relatively restricted voltage variation for each pulse may be expected for CUP or CDN.

Therefore the internal current sink gives rise to a slower compensation, thereby enhancing the sensitivity of the sensor. On the contrary, when CCP experiences a decrease, causes the sensor sensitivity to go down.





An in-built counter stage monitors the sensor triggers and correspondingly counts the pulses across CUP or CDN, the counter gets reset each time the pulse direction across the CUP to CDN alternates or changes.
The output pin represented as OUT undergoes an activation only when adequate number of pulses across CUP or CDN  are detected. Modest levels of interference or slow interactions across the sensor or input capacitance does not produce any effect on the output triggering.


The chip makes note of several conditions such as unequal charge/discharge patterns so that a confirmed output switching is rendered and spurious detection are eliminated.


The IC includes an advanced start-up circuitry which enables the chip to reach equilibrium rather quickly as soon as the supply to it is switched ON.


Internally the pin OUT is configured as an open drain which initiates the pinout with a high logic (Vdd) with a maximum of 20mA current for an attached load. In case the output is subjected with loads over 30mA, the supply is instantly disconnected due to the short circuit protection feature which is instantly triggered.
This pinout is also CMOS compatible and therefore becomes appropriate for all CMOS based loads or circuit stages.

As mentioned earlier, the sampling rate parameter "fs" relates itself as 50% of the frequency employed with the RC timing network. The sampling rate can be set across a predetermined span by appropriately fixing the value of CCLIN.

An internally modulated oscillator frequency at 4% through a pseudo-random-signal inhibits any chance of interferences from surrounding AC frequencies.

The IC also features a useful "output state selection mode" which can be used for enabling the output pin to either in the monostable or bistable state in response to the capacitive sensing of the input pinout. Its rendered in the following manner:

Mode#1 (TYPE enabled at Vss): The output is rendered active for sp long as the input is held under the external capacitive influence.

Mode#2 (TYPE enabled at VDD/NTRESD): In this mode the output is alternately switched ON and OFF (high and low) in response to subsequent capacitive interaction across the sensor foil.

Mode#3 (CTYPE enabled between TYPE and VSS): With this condition the output pin is triggered (low) for some predetermined length of time in response to each capacitive touch inputs, whose duration is proportional to the value of CTYPE and can be varied with a rate of 2.5ms per nF capacitance.


A standard value for CTYPE for getting around a 10ms delay in mode#3 could be 4.7nF, and the maximum permissible value for CTYPE being 470nF, which may result in with a delay of about a second. Any abrupt capacitive interventions or influences during this period are simply ignored. 

Reference: PCF8883 data sheet

This first part of the proposed 4kva synchronized stackable inverter circuit discusses how to implement the crucial automatic synchronization across the 4 inverters with regards to frequency, phase and voltage to keep the inverters running independent of each other yet achieving an output thats on par with each other.


The idea was requested by Mr. David. The following email conversation between him and me details the main specs of the proposed Synchronized 4kva Stackable Inverter Circuit.


Email#1

Hi Swagatam,

Firstly I wanted to say thank you for your contribution to the world at large, the information and most importantly your willingness to share your knowledge to help other people in my opinion is invaluable for many reasons.

I would like to enhance some of the circuits you have shared to suit my own purposes, unfortunately whilst I understand what is going on in the circuits I lack the creativity and knowledge to make the amendments myself. 

I can generally follow circuits if they are small and I can see where they join/connect into bigger schematics. If I may I would like to try to explain what I would like to achieve, though I am under no illusion that you are a very busy person and would not like take up your precious time unnecessarily. 

 The final goal would be that I would like to build ( assemble the components ) of a multi-source renewable energy micro grid, using Solar PV, Windmills, and bio diesel generators. 

 The first step is the PV solar inverter enhancements. I would like to use your 48 volt pure sine wave inverter circuit capable of maintaining a constant 2kW 230V output, it must be capable of delivering at least 3 times this output for a very short duration. 

The key modification that I want to achieve it to create a number of these inverters units to work in parallel and connected to an AC bus bar. I would like each inverter to independently and constantly sample the AC bus bar for frequency, voltage and current (load). 

I will call these inverters slave units. The idea being the invert modules will be “plug and play”. 

The inverter once connected to the AC bus bar would constantly sample/measure the frequency on the AC bus bar and use this information to drive the input of a 4047 IC such that its clock output can be advanced or retarded until it exactly clones the frequency on the AC bus bar once the two wave forms are synchronized the inverter will close a contactor or relay which connects the invert output stage to the AC bus bar. 

In the event that the frequency on the bar or the voltage moves outside of a pre-determined tolerance the inverter module should open the relay or contactor on the output stage effectively disconnecting the inverter output stage from the AC bar to protect its self. 

Additionally once connected to the AC bus bar the slave units would go to sleep or at least the output stage of the inverter would sleep while the load on the bar is less than the sum of all of the slave inverters. Imagine if you will there are 3 slave inverters attached to the AC bus bar, however the load on the bar is only 1.8kW then the other two slaves would go to sleep. 

The reciprocal would also be true that if the load on the bar jumped to say 3kW one of the sleeping inverts would instantly wake (already be in sync) to supply the additionally required energy. 

I imagine some large capacitors on each of the output stage would supply the energy required whilst the inverter has the very short moment whilst it wakes up. It would be preferable (only in my opinion) not to directly connect each inverter to each other but rather that they be independently autonomous. 

I want to try to avoid micro controllers or the units error or fault checking each other or the units having ‘address’s’ on the system. In my mind’s eye I imagine that the first connected device on the AC bus bar would be a very stable reference inverter that is constantly connected. 

This reference inverter would provide the frequency and voltage that the other slave units would use to generate their own respective outputs. 

Unfortunately I can’t get my head around how you could prevent a feedback loop where the slave units would each potentially end up becoming the reference unit. Beyond the scope of this email I have some small generators I would like to connect to the AC bus bar synchronizing to the reference inverter to supply energy in the event that the load exceeds the DC max output capacity. 

The overall premise is that the load presented to the AC bus bar would determine how many inverters and ultimately how many generators would either autonomously connect or disconnect to meet the demand as this would hopefully save energy or at least not waste energy. 

The system being completely built of multiple modules would then be expandable/contractible as well as robust/resilient such that if anyone or perhaps two units were to fail the system would continue to function all be it at reduced capacity. I have attached a block diagram and excluded the battery charging for the time being. 

I plan on charging the battery bank from the AC bus and rectifying down to 48V DC this way I can charge from the generators or the renewable energy sources, I do recognize that this is perhaps not as efficient as using DC mppt but I think what I lose in efficiency I gain in flexibility. I live a long way from town or the utility grid. 

 For reference there would be a minimum constant load on the AC bus bar of 2kW’s though the peak load could rise by as much as 30kW. 

My plan is for the 1st 10 to 15kW to be provided by the solar PV panels and two 3kW (peak) windmills the windmills are wild AC rectified to DC and a 1000Ah 48 volt battery bank. (Which I would like to avoid draining/discharging beyond 30% of its capacity to ensure battery life) the remaining infrequent and very intermittent energy demand would be satisfied by my generators. 

This infrequent and intermittent load comes from my workshop. 

I have been thinking that it may be prudent to build a capacitor bank to handle or pick up the system slack of any inductive load start up currents such as the motor on my air compressor and table saw. 

But I am not sure at this time if there is not a better/cheaper way. Your thoughts and comments would be greatly appreciated and valued I hope you have time to get back to me. Thank you for your time and attention in advance. 

Kind Regards 
David 
Sent from my BlackBerry® wireless device

My Reply

Hi David,

I have read your requirement and have hopefully understood it correctly.

Out of the 4 inverters, only one would be having its own frequency
generator, while others would be running by extracting the frequency from
this main inverter output, and thus all would be in sync with each other
and with this master inverters specs.

Ill try to design it and hope it works as expected and as per your
mentioned specs, however the implementation will need to be done by an
expert who should be capable of understanding the concept and modify/tweak
it to perfection wherever it might be required....otherwise succeeding
with this reasonably complex design could become extremely difficult.

I can only present the basic concept and the schematic....rest will need
to be done by the engineers from your side.

It might take me some time to complete, this since I already have many
pending requests in the Queue...Ill inform you as son as its posted

Best Regards
Swag

Email#2





























My Reply

Thanks David,

Basically you want the inverters to be in sync with each other in terms of
frequency and phase, and also each one having the ability to become the
master inverter and takeover the charge, in case the previous one fails
due to some reason. Right?

Ill try to fix this with whatever knowledge I have and some common sense
and not by employing complex ICs or configurations.

Warmest Regards
Swag

Email#3











The Design

As requested by Mr. David, the proposed 4kva stackable power inverter circuits need to be in the form of 4 separate inverter circuits, which can be stacked up appropriately in sync with each other for supplying the correct amount of self-regulating power to the connected loads, depending on how these loads are switched ON and OFF.

Synchronizing the Inverters

The basic design for fulfilling the mentioned criteria is shown in the following diagram:





This is in fact done by integrating the the "slave" inverters through an opamp/optocoupler stage as indicated in the above design.

Initially, the master inverter#1 is switched ON, which allows the opamp 741 stage to get powered and to initialize the frequency and phase tracking of the output voltage.

Once this is initiated, the subsequent inverters are all switched ON for adding power to the mains line.

As can be seen the opamp output is connected with the timing capacitor of all the slave inverters through an opto coupler which force the slave inverters to follow the frequency and the phase angle of the master inverter.

However the interesting thing here is the latching factor of the opamp with the instantaneous phase and frequency information. This happens since all the inverters are now delivering and running at the specified frequency and phase from the master inverter, which implies if in case any of the inverters fail including the master inverter, the opamp is able to quickly track and inject the instantaneous frequency/phase info and force the existing inverters to run with this specifications, and the inverter in turn are able to sustain the feedbacks to the opamp stage to make the transitions seamless and self optimizing.

 Therefore hopefully the opamp stage takes care of the first challenge of keeping all the proposed stackable inverters perfectly synchronized through a LIVE tracking of the available mains specification.

In the next part of the article well learn the synchronized PWM sinewave stage, which is the next crucial feature of the above discussed design. 

Data provided by: Mr. hisham bahaa-aldeen (hisham2630@gmail.com)


Sinewave UPS Circuit using PIC16F72 Part-1

Sinewave UPS Circuit using PIC16F72 Part-2
 
Sinewave UPS Circuit using PIC16F72 Part-4

LOW BATTERY PROTECTION:

While the controller operates in the inverter-mode it repeatedly monitors the voltage at its pin4 (BATT SENSE), pin7 (OVER LOAD sense) and pin2 (AC MAIN sense).


Should the voltage at pin4 rise above 2.6V the controller would take no notice of it and may be seen escaping to supplementary sensing-mode, but as soon as the voltage here drops to around 2.5V the controller stage would prohibit its functioning at this point, switching OFF the inverter-mode such that the low battery LED turns ON and prompting the buzzer to beep.

OVER LOAD:

Over load protection is a mandatory functionality implemented in most inverter systems. Up here, in order to cut-of the inverter in the event the load goes beyond the safe load specifications, the battery current is first detected across the negative line (i.e the voltage drop across the fuse and negative path of the low side MOSFET bank) and this greatly reduced voltage (in mV) is proportionately intensified by the comparator U5 (composing of pins12,13 1nd 14)  (make reference to circuit diagram).



This amplified voltage output from pin14 of comparator (U5) is rigged as inverting amplifier and applied to pin7 of the microcontroller.

The software compares the voltage with the reference, which is for this particular pin is 2V. Quite as talked over previously the controller senses the voltages in this pin besides operating the system in the inverter-mode, every time the load current augments the voltage at this pin builds up, whenever the voltage on pin7 of the controller IC is above 2V the process shuts off the inverter and switches to overload mode, shutting off the inverter, turning ON the overload LED and causing the buzzer to beep, which after 9-beeps prompts the inverter to switched-ON again, inspecting the voltage at pin7 for a second time, suppose in case the controller identifies pin7 voltage to be below 2V, it then operates the inverter on normal mode, other wise it disconnects the inverter yet again, and this process is known as the auto-reset-mode.




Like in this article we articulated beforehand that when in  inverter-mode, the controller reads the voltage at its pin4 (for Low-batt), pin7 (for overload) and pin2 for AC main voltage status. We comprehend that the system may be functioning in twin mode (a) UPS mode,(b) inverter mode.

So before inspecting the pin2 voltage of PIC the routine before anything else confirms at what mode the unit may be working by sensing the high/lo logic at pin16 of the PIC.

Inverter to mains changeover (INV-MODE): 

In this particular mode as soon as the AC main voltage is detected to be in the vicinity of 140V AC, the changeover action can be seen implemented, this voltage threshold is pre-settable by the user, implies that in cases where the pin2 voltage is above 0.9V, the controller IC may shut off the inverter and switch to mains-on mode, where the system examines the pin2 voltage to test the AC mains failure and maintain the charging process, which in this article we will be explaining later on.

Inverter to Battery changeover (UPS-MODE): 

Within this setting each time the AC main voltage is in the vicinity of 190V AC the changeover may be seen enforcing to battery mode, this voltage threshold is also software pre-setteble, meaning when ever the pin2 volage is above 1.22V the controller may be expected to switch ON the inverter and switched to battery routine wherein the system inspects the pin2 voltage to verifies the AC mains absence and operates the charging schedule which we would be discussing further down in the article.