Showing posts with label precision. Show all posts
Showing posts with label precision. Show all posts
Sunday, October 2, 2016
Precision Capacitive Touch Proximity Sensor Circuit Part 2
Precision Capacitive Touch Proximity Sensor Circuit Part 2
The previous post explained the datasheet of the precision capacitive touch/proximity sensor IC PCF8883, here we learn a typical circuit configuration using the same IC which can be applied in all products requiring precision remote touch stimulated operations.
The proposed capacitive touch and proximity sensor may be diversely used in many different applications as indicated in the following data:
A typical application configuration using the IC can be witnessed below:
The + input supply is attached with the VDD. A smoothing capacitor may be preferably connected across and VDD and ground and also across VDDUNTREGD and ground for more reliable working of the chip.
The capacitance value of COLIN as produced on pin CLIN fixes the sampling rate effectively. Increasing sampling rate may enable enhance reaction time on the sensing input with a proportionate increase in the current consumption
The sensing capacitive touch plate could be in the form of a miniature metal foil or plate shielded and isolated with a non conductive layer.
This sensing area could be either terminated over a longer distances via a coaxial cable CCABLE whose other ends may be linked with the IN of the IC, or the plate could be simply directly connected with the INpinout of the IC depending on the application needs.
The IC is equipped with an internal low pass filter circuitry which helps to suppress all forms of RF interferences that may try to make way in to the IC through the IN pin of the IC.
Additionally as indicated in the diagram one may also add an external configuration using RF and CF to further enhance the RF suppression and reinforce RF immunity for the circuit.
In order to achieve an optimal performance from the circuit, its recommended that the sum of the capacitance values of CSENSE + CCABLE + Cp should be within a given appropriate range, a good level could be around 30pF.
This helps the control loop to work in a better way with the static capacitance over CSENSE for equalizing the rather slower interactions on the sensing capacitive plate.
For achieving an increased levels of capacitive inputs it may be recommended to include a supplementary resistor Rc as indicated in the diagram which helps to control the discharge time as per the internal timing requirement specs.
The cross sectional area of the attached sensing plate or a sensing foil becomes directly proportional to the sensitivity of the circuit, in conjunction with the value of the capacitor Ccpc, reducing Ccpc value can greatly affect the sensitivity of the sensing plate. Therefore for achieving an effective amount of sensitivity, Ccpc could be increased optimally and accordingly.
The pinout marked CPC is internally attributed with a high impedance and therefore could be susceptible to leakage currents.
Make sure that Ccpc is chosen with a high quality PPC of MKT type of capacitor or X7R type for obtaining optimal performance from the design.
In case the system is intended to be operated with a restricted input capacitance of upto 35pF and at freezing temperatures -20 degrees C, then it may be advisable to bring down the supply voltage to the IC to around 2.8V. This in turn brings down the operating range of Vlicpc voltage whose specification lies between 0.6V to VDD - 0.3V.
Moreover, lowering the operating range of Vucpc could result in lowering the input capacitance range of the circuit proportionately.
Also, one may notice that as Vucpc value increases with decreasing temperatures as demonstrated in the diagrams, which tells us why appropriately lowering the supply voltage helps in decreasing temperatures.
Table 6 and Table7 indicates the recommended range of the components values which may be appropriately chosen as per the desired application specifications with reference to the above instructions.
Reference: PCF8883 data sheet
The proposed capacitive touch and proximity sensor may be diversely used in many different applications as indicated in the following data:
A typical application configuration using the IC can be witnessed below:
The + input supply is attached with the VDD. A smoothing capacitor may be preferably connected across and VDD and ground and also across VDDUNTREGD and ground for more reliable working of the chip.
The capacitance value of COLIN as produced on pin CLIN fixes the sampling rate effectively. Increasing sampling rate may enable enhance reaction time on the sensing input with a proportionate increase in the current consumption
The sensing capacitive touch plate could be in the form of a miniature metal foil or plate shielded and isolated with a non conductive layer.
This sensing area could be either terminated over a longer distances via a coaxial cable CCABLE whose other ends may be linked with the IN of the IC, or the plate could be simply directly connected with the INpinout of the IC depending on the application needs.
The IC is equipped with an internal low pass filter circuitry which helps to suppress all forms of RF interferences that may try to make way in to the IC through the IN pin of the IC.
Additionally as indicated in the diagram one may also add an external configuration using RF and CF to further enhance the RF suppression and reinforce RF immunity for the circuit.
In order to achieve an optimal performance from the circuit, its recommended that the sum of the capacitance values of CSENSE + CCABLE + Cp should be within a given appropriate range, a good level could be around 30pF.
This helps the control loop to work in a better way with the static capacitance over CSENSE for equalizing the rather slower interactions on the sensing capacitive plate.
For achieving an increased levels of capacitive inputs it may be recommended to include a supplementary resistor Rc as indicated in the diagram which helps to control the discharge time as per the internal timing requirement specs.
The cross sectional area of the attached sensing plate or a sensing foil becomes directly proportional to the sensitivity of the circuit, in conjunction with the value of the capacitor Ccpc, reducing Ccpc value can greatly affect the sensitivity of the sensing plate. Therefore for achieving an effective amount of sensitivity, Ccpc could be increased optimally and accordingly.
The pinout marked CPC is internally attributed with a high impedance and therefore could be susceptible to leakage currents.
Make sure that Ccpc is chosen with a high quality PPC of MKT type of capacitor or X7R type for obtaining optimal performance from the design.
In case the system is intended to be operated with a restricted input capacitance of upto 35pF and at freezing temperatures -20 degrees C, then it may be advisable to bring down the supply voltage to the IC to around 2.8V. This in turn brings down the operating range of Vlicpc voltage whose specification lies between 0.6V to VDD - 0.3V.
Moreover, lowering the operating range of Vucpc could result in lowering the input capacitance range of the circuit proportionately.
Also, one may notice that as Vucpc value increases with decreasing temperatures as demonstrated in the diagrams, which tells us why appropriately lowering the supply voltage helps in decreasing temperatures.
Table 6 and Table7 indicates the recommended range of the components values which may be appropriately chosen as per the desired application specifications with reference to the above instructions.
Reference: PCF8883 data sheet
Available link for download
Friday, September 30, 2016
Precision Capacitive Touch Proximity Sensor Circuit Part 1
Precision Capacitive Touch Proximity Sensor Circuit Part 1
The IC PCF8883 is designed to work like a precision capacitive touch and proximity sensor switch through a unique (EDISEN patented) digital technology for sensing the minutest difference in the capacitance around its specified sensing plate.
The main features of this specialized capacitive touch and proximity sensor can be studies as given below:
The following image shows the internal configuration of the IC PCF8883
The IC doesnt rely on the traditional dynamic capacitance mode of sensing rather detects the variation in the static capacitance by employing automatic correction through continuous auto-calibration.
The sensor is basically in the form of a small conductive foil which may be directly integrated with the relevant pinouts of the IC for the intended capacitive sensing or perhaps terminated to longer distances through coaxial cables for enabling accurate and effective remote capacitive touch sensing operations
The following figures represent the pinout details of the IC PCF8883. The detailed functioning of the various pinouts and the in-built circuitry may be understood with the following points:
The pinout IN which is supposed to be connected with the external capacitive sensing foil is linked with the ICs internal RC network.
The discharge time given by "tdch" of the RC network is compared by the discharge time of the second in-bult RC network denoted as "tdchimo".
The two RC networks go through periodic charging by VDD(INTREGD) through a couple of identical and synchronized switch networks, and subsequently discharged with the help of a resistor to Vss or the ground
The rate at which this charge discharge is executed is regulated by a sampling rate denoted by "fs".
In case if the potential difference is seen to be dropping below the internally set reference voltage VM, the corresponding output of the comparator tends to become low. The logic level which follows the comparators identifies the exact comparator that actually could switch before the other.
And if the upper comparator is identified to have fired first, this results with a pulse being rendered on CUP, whereas if the lower comparator is detected to have switched prior to the upper, then the pulse is enabled at CDN.
The above pulses engage in controlling the charge level over the external capacitor Ccpc associated with pin CPC. When a pulse is generated on CUP, the Ccpc is charged through VDDUNTREGD for a given period of time which triggers a rising potential on Ccpc.
Quite on the same lines, when a pulse is rendered at CDN, the Ccpc gets linked with current sink device to ground which discharges the capacitor causing its potential to collapse.
Whenever the capacitance at pin IN gets higher, it correspondingly increases the discharge time tdch, which causes the voltage across the relevant comparator to fall at a correspondingly longer time. When this takes place the output of the comparator tends to get low which in turn renders a pulse at CDN forcing the external capacitor CCP to discharge to some smaller degree.
This implies that CUP now generates the majority of the pulses which causes CCP to charge up even more without going through any further steps.
Inspite of this, the automatic voltage controlled calibration feature of the IC which relies on a sink current regulation "ism" associated with pin IN makes an effort to balance out the discharge time tdch by referring it with an internally set discharge time tdcmef.
The voltage across Ccpg is current controlled and becomes responsible for the discharge of the capacitance on IN rather rapidly whenever the potential across CCP is detected to be increasing. This perfectly balances the increasing capacitance on input pin IN.
This effect give rise to a closed loop tracking system which continuously monitors and engages into an automatic equalizing of the discharge time tdch with reference to tdchlmf.
This helps to correct sluggish variations in capacitance across IN pinout of the IC. During rapidly charging sates for example when a human finger is approached the sensing foil quickly, the discussed compensation might not transpire, in equilibrium conditions the length of the discharge period do not differ causing the pulse to alternately fluctuate across CUP and CDN.
This further implies that with larger Ccpg values a relatively restricted voltage variation for each pulse may be expected for CUP or CDN.
Therefore the internal current sink gives rise to a slower compensation, thereby enhancing the sensitivity of the sensor. On the contrary, when CCP experiences a decrease, causes the sensor sensitivity to go down.
An in-built counter stage monitors the sensor triggers and correspondingly counts the pulses across CUP or CDN, the counter gets reset each time the pulse direction across the CUP to CDN alternates or changes.
The output pin represented as OUT undergoes an activation only when adequate number of pulses across CUP or CDN are detected. Modest levels of interference or slow interactions across the sensor or input capacitance does not produce any effect on the output triggering.
The chip makes note of several conditions such as unequal charge/discharge patterns so that a confirmed output switching is rendered and spurious detection are eliminated.
The IC includes an advanced start-up circuitry which enables the chip to reach equilibrium rather quickly as soon as the supply to it is switched ON.
Internally the pin OUT is configured as an open drain which initiates the pinout with a high logic (Vdd) with a maximum of 20mA current for an attached load. In case the output is subjected with loads over 30mA, the supply is instantly disconnected due to the short circuit protection feature which is instantly triggered.
This pinout is also CMOS compatible and therefore becomes appropriate for all CMOS based loads or circuit stages.
As mentioned earlier, the sampling rate parameter "fs" relates itself as 50% of the frequency employed with the RC timing network. The sampling rate can be set across a predetermined span by appropriately fixing the value of CCLIN.
An internally modulated oscillator frequency at 4% through a pseudo-random-signal inhibits any chance of interferences from surrounding AC frequencies.
The IC also features a useful "output state selection mode" which can be used for enabling the output pin to either in the monostable or bistable state in response to the capacitive sensing of the input pinout. Its rendered in the following manner:
Mode#1 (TYPE enabled at Vss): The output is rendered active for sp long as the input is held under the external capacitive influence.
Mode#2 (TYPE enabled at VDD/NTRESD): In this mode the output is alternately switched ON and OFF (high and low) in response to subsequent capacitive interaction across the sensor foil.
Mode#3 (CTYPE enabled between TYPE and VSS): With this condition the output pin is triggered (low) for some predetermined length of time in response to each capacitive touch inputs, whose duration is proportional to the value of CTYPE and can be varied with a rate of 2.5ms per nF capacitance.
A standard value for CTYPE for getting around a 10ms delay in mode#3 could be 4.7nF, and the maximum permissible value for CTYPE being 470nF, which may result in with a delay of about a second. Any abrupt capacitive interventions or influences during this period are simply ignored.
Reference: PCF8883 data sheet
The main features of this specialized capacitive touch and proximity sensor can be studies as given below:
The following image shows the internal configuration of the IC PCF8883
The IC doesnt rely on the traditional dynamic capacitance mode of sensing rather detects the variation in the static capacitance by employing automatic correction through continuous auto-calibration.
The sensor is basically in the form of a small conductive foil which may be directly integrated with the relevant pinouts of the IC for the intended capacitive sensing or perhaps terminated to longer distances through coaxial cables for enabling accurate and effective remote capacitive touch sensing operations
The following figures represent the pinout details of the IC PCF8883. The detailed functioning of the various pinouts and the in-built circuitry may be understood with the following points:
A typical application configuration can be studied through this capacitive touch/proximity sensorcircuit design
The pinout IN which is supposed to be connected with the external capacitive sensing foil is linked with the ICs internal RC network.
The discharge time given by "tdch" of the RC network is compared by the discharge time of the second in-bult RC network denoted as "tdchimo".
The two RC networks go through periodic charging by VDD(INTREGD) through a couple of identical and synchronized switch networks, and subsequently discharged with the help of a resistor to Vss or the ground
The rate at which this charge discharge is executed is regulated by a sampling rate denoted by "fs".
In case if the potential difference is seen to be dropping below the internally set reference voltage VM, the corresponding output of the comparator tends to become low. The logic level which follows the comparators identifies the exact comparator that actually could switch before the other.
And if the upper comparator is identified to have fired first, this results with a pulse being rendered on CUP, whereas if the lower comparator is detected to have switched prior to the upper, then the pulse is enabled at CDN.
The above pulses engage in controlling the charge level over the external capacitor Ccpc associated with pin CPC. When a pulse is generated on CUP, the Ccpc is charged through VDDUNTREGD for a given period of time which triggers a rising potential on Ccpc.
Quite on the same lines, when a pulse is rendered at CDN, the Ccpc gets linked with current sink device to ground which discharges the capacitor causing its potential to collapse.
Whenever the capacitance at pin IN gets higher, it correspondingly increases the discharge time tdch, which causes the voltage across the relevant comparator to fall at a correspondingly longer time. When this takes place the output of the comparator tends to get low which in turn renders a pulse at CDN forcing the external capacitor CCP to discharge to some smaller degree.
This implies that CUP now generates the majority of the pulses which causes CCP to charge up even more without going through any further steps.
Inspite of this, the automatic voltage controlled calibration feature of the IC which relies on a sink current regulation "ism" associated with pin IN makes an effort to balance out the discharge time tdch by referring it with an internally set discharge time tdcmef.
The voltage across Ccpg is current controlled and becomes responsible for the discharge of the capacitance on IN rather rapidly whenever the potential across CCP is detected to be increasing. This perfectly balances the increasing capacitance on input pin IN.
This effect give rise to a closed loop tracking system which continuously monitors and engages into an automatic equalizing of the discharge time tdch with reference to tdchlmf.
This helps to correct sluggish variations in capacitance across IN pinout of the IC. During rapidly charging sates for example when a human finger is approached the sensing foil quickly, the discussed compensation might not transpire, in equilibrium conditions the length of the discharge period do not differ causing the pulse to alternately fluctuate across CUP and CDN.
This further implies that with larger Ccpg values a relatively restricted voltage variation for each pulse may be expected for CUP or CDN.
Therefore the internal current sink gives rise to a slower compensation, thereby enhancing the sensitivity of the sensor. On the contrary, when CCP experiences a decrease, causes the sensor sensitivity to go down.
An in-built counter stage monitors the sensor triggers and correspondingly counts the pulses across CUP or CDN, the counter gets reset each time the pulse direction across the CUP to CDN alternates or changes.
The output pin represented as OUT undergoes an activation only when adequate number of pulses across CUP or CDN are detected. Modest levels of interference or slow interactions across the sensor or input capacitance does not produce any effect on the output triggering.
The chip makes note of several conditions such as unequal charge/discharge patterns so that a confirmed output switching is rendered and spurious detection are eliminated.
The IC includes an advanced start-up circuitry which enables the chip to reach equilibrium rather quickly as soon as the supply to it is switched ON.
Internally the pin OUT is configured as an open drain which initiates the pinout with a high logic (Vdd) with a maximum of 20mA current for an attached load. In case the output is subjected with loads over 30mA, the supply is instantly disconnected due to the short circuit protection feature which is instantly triggered.
This pinout is also CMOS compatible and therefore becomes appropriate for all CMOS based loads or circuit stages.
As mentioned earlier, the sampling rate parameter "fs" relates itself as 50% of the frequency employed with the RC timing network. The sampling rate can be set across a predetermined span by appropriately fixing the value of CCLIN.
An internally modulated oscillator frequency at 4% through a pseudo-random-signal inhibits any chance of interferences from surrounding AC frequencies.
The IC also features a useful "output state selection mode" which can be used for enabling the output pin to either in the monostable or bistable state in response to the capacitive sensing of the input pinout. Its rendered in the following manner:
Mode#1 (TYPE enabled at Vss): The output is rendered active for sp long as the input is held under the external capacitive influence.
Mode#2 (TYPE enabled at VDD/NTRESD): In this mode the output is alternately switched ON and OFF (high and low) in response to subsequent capacitive interaction across the sensor foil.
Mode#3 (CTYPE enabled between TYPE and VSS): With this condition the output pin is triggered (low) for some predetermined length of time in response to each capacitive touch inputs, whose duration is proportional to the value of CTYPE and can be varied with a rate of 2.5ms per nF capacitance.
A standard value for CTYPE for getting around a 10ms delay in mode#3 could be 4.7nF, and the maximum permissible value for CTYPE being 470nF, which may result in with a delay of about a second. Any abrupt capacitive interventions or influences during this period are simply ignored.
Reference: PCF8883 data sheet
Available link for download
Wednesday, August 24, 2016
Precision Water Management in Irrigation Systems Circuit Design
Precision Water Management in Irrigation Systems Circuit Design
The article presents a simple circuit idea which can be used for implementing an efficient water management and control in farms and irrigation systems.
The idea was requested by Mr. Ajinkya Sonwane, Mr. Akshay Kokane and Mr. Kunal Raut, studying in AISSMS IOIT College of Engineering.
The idea was requested by Mr. Ajinkya Sonwane, Mr. Akshay Kokane and Mr. Kunal Raut, studying in AISSMS IOIT College of Engineering.
As per the request, water needs to be controlled and managed at a given predetermined rate depending on the type of crop and its necessity.
The easiest possible solution to this could be in the form of solenoid timers which could be programmed once by the farmers for enabling an automatic water management, everyday, without any further intervention, until the crop or season changes. The timer is supposed to be extremely flexible, easy to operate and cost effective.
The idea here is to connect DC solenoids valves at different nodes of the distribution pipe network and control these solenoid valves using timers.
The timer controller unit could be positioned in a specific position (control room) for enabling the farmers to set the timing as per the needs anytime, as required, and the signals could be appropriately transmitted to the relevant valves through wires for executing the controlled release of water across the given area.
The following circuit idea using the IC 4060 may be considered perfectly suitable for the proposed precision water management in irrigation system.
The circuit functioning can be understood with the help of the following points:
The IC 4060 can be seen configured in its standard timer/oscillator mode.
Pin#10 and pin#9 are associated with the time delay setting for the output pinouts 3, 13, 14 and 15.
The SW1 switch facilitates the time delay selection through the respective resistors which decides for how long the output of the IC may be rendered active, ensuring that the connected solenoid valve stays switched ON and in a water supplying mode only during this period of time.
The indicated timing resistors for SW1 are arbitrarily arranged and must be appropriately calculated during the actual implementation as per the crop specifications, and water availability.
SW1 is specified for a 4 position selection which can be increased to more positions by simply using a switch with more number of contacts and by adding subsequent number of resistors in the appropriate order.
SW2 is also a rotary switch identical to SW1 and is positioned for selecting the switching mode of the solenoid valve.
Pin#3 provides a continuous ON mode for the valve for the selected time slot after which the valve is switched off until the next day, whereas pin13, 14, 15 provides an oscillating (ON/OFF/ON/OFF) activation mode for the solenoid so that the water is managed in a more controlled manner, however this may be optional if the valve nozzle is correctly dimensioned for a restricted flow as per the given criteria.
The whole system can be seen powered through a small solar panel which makes the entire system full automatic.
When dawn sets in, the solar panel voltage gradually rises and at a particular point reaches a 12V level activating the connected relay.
The relay contacts instantly connect the solar voltage with the circuit initializing the procedure wherein the IC pin#12 is reset by C2 forcing the IC to begin counting from zero.
All the outputs are rendered with a zero logic initially which makes sure that the TIP127 transistor commences with a switch ON condition and triggers the connected solenoid valve.
If SW2 is positioned with pin#3, the TIP127 and the valve stay switched ON continuously supplying water through the nozzle in a dripping manner until the set timing is elapsed and pin#3 becomes high.
As soon as pin#3 goes high the logic high instantly latches pin#11 of the IC and stops the IC from any further counting, freezing the procedure permanently for the day. The logic high is also transferred to the base of the TIP127 switching it OFF along with the valve system. The water supply to the crops at this moment gets halted.
At dusk when the sunlight weakens and gets below the relay holding level, the relay is switched OFF which also switches OFF the associated circuit stages, until the next day when the procedure undergoes the triggering of a fresh cycle.
PB1 is used for resetting the proceedings at anytime for enabling a new start for the circuit.
Many number of the above explained systems can be implemented at the specified nodes of the distribution pipe for achieving the desired precision water management in irrigation systems.
How to Calculate the Timing Resistors
The timing resistors associated with SW1 can be calculated with some experimentation as given below:
Any arbitrarily selected resistor may be initially switched with SW1, say for example we choose the 100k resistor as the reference.
Now switch ON the circuit to initiate the procedures, the red LED will be seen coming ON.
As soon as the circuit initiates monitor the timing using a stop watch or a clock and watch when the green LED turns ON switching OFF the red LED.
Note the timing achieved using the particular resistor which is 100K in this case.
Lets say it resulted in a delay period of 450 seconds, then taking this as the yardstick other values could be simply determined through a simple cross multiplication as given below:
100/R = 450/t
where R stands for the other unknown resistor value and "t" is the desired time delay for the solenoid valve.
The easiest possible solution to this could be in the form of solenoid timers which could be programmed once by the farmers for enabling an automatic water management, everyday, without any further intervention, until the crop or season changes. The timer is supposed to be extremely flexible, easy to operate and cost effective.
The idea here is to connect DC solenoids valves at different nodes of the distribution pipe network and control these solenoid valves using timers.
The timer controller unit could be positioned in a specific position (control room) for enabling the farmers to set the timing as per the needs anytime, as required, and the signals could be appropriately transmitted to the relevant valves through wires for executing the controlled release of water across the given area.
The following circuit idea using the IC 4060 may be considered perfectly suitable for the proposed precision water management in irrigation system.
The circuit functioning can be understood with the help of the following points:
The IC 4060 can be seen configured in its standard timer/oscillator mode.
Pin#10 and pin#9 are associated with the time delay setting for the output pinouts 3, 13, 14 and 15.
The SW1 switch facilitates the time delay selection through the respective resistors which decides for how long the output of the IC may be rendered active, ensuring that the connected solenoid valve stays switched ON and in a water supplying mode only during this period of time.
The indicated timing resistors for SW1 are arbitrarily arranged and must be appropriately calculated during the actual implementation as per the crop specifications, and water availability.
SW1 is specified for a 4 position selection which can be increased to more positions by simply using a switch with more number of contacts and by adding subsequent number of resistors in the appropriate order.
SW2 is also a rotary switch identical to SW1 and is positioned for selecting the switching mode of the solenoid valve.
Pin#3 provides a continuous ON mode for the valve for the selected time slot after which the valve is switched off until the next day, whereas pin13, 14, 15 provides an oscillating (ON/OFF/ON/OFF) activation mode for the solenoid so that the water is managed in a more controlled manner, however this may be optional if the valve nozzle is correctly dimensioned for a restricted flow as per the given criteria.
The whole system can be seen powered through a small solar panel which makes the entire system full automatic.
When dawn sets in, the solar panel voltage gradually rises and at a particular point reaches a 12V level activating the connected relay.
The relay contacts instantly connect the solar voltage with the circuit initializing the procedure wherein the IC pin#12 is reset by C2 forcing the IC to begin counting from zero.
All the outputs are rendered with a zero logic initially which makes sure that the TIP127 transistor commences with a switch ON condition and triggers the connected solenoid valve.
If SW2 is positioned with pin#3, the TIP127 and the valve stay switched ON continuously supplying water through the nozzle in a dripping manner until the set timing is elapsed and pin#3 becomes high.
As soon as pin#3 goes high the logic high instantly latches pin#11 of the IC and stops the IC from any further counting, freezing the procedure permanently for the day. The logic high is also transferred to the base of the TIP127 switching it OFF along with the valve system. The water supply to the crops at this moment gets halted.
At dusk when the sunlight weakens and gets below the relay holding level, the relay is switched OFF which also switches OFF the associated circuit stages, until the next day when the procedure undergoes the triggering of a fresh cycle.
PB1 is used for resetting the proceedings at anytime for enabling a new start for the circuit.
Many number of the above explained systems can be implemented at the specified nodes of the distribution pipe for achieving the desired precision water management in irrigation systems.
How to Calculate the Timing Resistors
The timing resistors associated with SW1 can be calculated with some experimentation as given below:
Any arbitrarily selected resistor may be initially switched with SW1, say for example we choose the 100k resistor as the reference.
Now switch ON the circuit to initiate the procedures, the red LED will be seen coming ON.
As soon as the circuit initiates monitor the timing using a stop watch or a clock and watch when the green LED turns ON switching OFF the red LED.
Note the timing achieved using the particular resistor which is 100K in this case.
Lets say it resulted in a delay period of 450 seconds, then taking this as the yardstick other values could be simply determined through a simple cross multiplication as given below:
100/R = 450/t
where R stands for the other unknown resistor value and "t" is the desired time delay for the solenoid valve.
Available link for download
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